The present invention relates to integrated circuit design, and more specifically, to an integrated circuit design layout optimizer based on process assumptions and/or actual variations and failure mechanisms.
Certain design rules or ground rules dictate the design of integrated circuits. Design rules are maintained and released by a semiconductor foundry for its customers (layout designers of integrated circuits) to follow. Conventionally, restrictive design rules (RDRs) are used that curtail some of the “freedom” layout designers have traditionally had with regular design rules in less advanced process technologies. To achieve and maintain an acceptable return on investment for its customers and by extension for itself, a foundry may be compelled, to adopt RDRs to better ensure the completed layout design of an integrated circuit is manufacturable with the desired yield in more advanced process technologies. Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. It is expected to be necessary for the upcoming 10 nm and 7 nm node semiconductor processes and beyond. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Hence, additional exposures would be needed, or else positioning patterns using etched feature sidewalls (using spacers) would be necessary.
Design Arc is a collection of design rules and the sum of these design rules is often multiple of the critical pitches of the technology. The critical pitch is a fixed and predetermined length due to process restriction. When the design arc is involved, the design space becomes discretized, which makes it very difficult to resolve design rules violations without area penalty.